CPUID
instruction (identified by a CPUID
opcode) is a processor supplementary instruction (its name derived from CPU IDentification) for the x86 architecture allowing software to discover details of the processor. It was introduced by Intel in 1993 when it introduced the Pentium and SL-enhanced 486 processors.[1]CPUID
to determine processor type and whether features such as MMX/SSE are implemented. CPUID
instruction, programmers would write esoteric machine code which exploited minor differences in CPU behavior in order to determine the processor make and model.[2][3]CPUID
instruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 CPUID instruction.CPUID
opcode is 0Fh, A2h (as two bytes, or A20Fh as a single word).CPUID
instruction takes no parameters as CPUID
implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. CPUID
should be called with EAX = 0
first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements.CPUID
should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID
with EAX = 80000000h
.CPUID
) is returned in EAX.Processors | Basic | Extended |
---|---|---|
Earlier Intel 486 | CPUID Not Implemented | |
Later Intel 486 and Pentium | 0x01 | Not Implemented |
Pentium Pro, Pentium II and Celeron | 0x02 | Not Implemented |
Pentium III | 0x03 | Not Implemented |
Pentium 4 | 0x02 | 0x8000 0004 |
Xeon | 0x02 | 0x8000 0004 |
Pentium M | 0x02 | 0x8000 0004 |
Pentium 4 with Hyper-Threading | 0x05 | 0x8000 0008 |
Pentium D (8xx) | 0x05 | 0x8000 0008 |
Pentium D (9xx) | 0x06 | 0x8000 0008 |
Core Duo | 0x0A | 0x8000 0008 |
Core 2 Duo | 0x0A | 0x8000 0008 |
Xeon 3000, 5100, 5200, 5300, 5400 series | 0x0A | 0x8000 0008 |
Core 2 Duo 8000 series | 0x0D | 0x8000 0008 |
Xeon 5200, 5400 series | 0x0A | 0x8000 0008 |
Atom | 0x0A | 0x8000 0008 |
Nehalem-based processors | 0x0B | 0x8000 0008 |
IvyBridge-based processors | 0x0D | 0x8000 0008 |
Skylake-based processors (proc base & max freq; Bus ref. freq) | 0x16 | 0x8000 0008 |
System-On-Chip Vendor Attribute Enumeration Main Leaf | 0x17 | 0x8000 0008 |
EAX | |||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Extended Family ID | Extended Model ID | Reserved | Processor Type | Family ID | Model | Stepping ID |
Type | Encoding in Binary |
---|---|
Original OEM Processor | 00 |
Intel Overdrive Processor | 01 |
Dual processor (not applicable to Intel486 processors) | 10 |
Reserved value | 11 |
Bits | EBX | Valid |
---|---|---|
7:0 | Brand Index | |
15:8 | CLFLUSH line size (Value . 8 = cache line size in bytes) | if CLFLUSH feature flag is set. CPUID.01.EDX.CLFSH [bit 19]= 1 |
23:16 | Maximum number of addressable IDs for logical processors in this physical package; The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package. Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.[6] | if Hyper-threading feature flag is set. CPUID.01.EDX.HTT [bit 28]= 1 |
31:24 | Local APIC ID: The initial APIC-ID is used to identify the executing logical processor. It can also be identified via the cpuid 0BH leaf ( CPUID.0Bh.EDX[x2APIC-ID] ). | Pentium 4 and subsequent processors. |
Bit | EDX | ECX | ||
---|---|---|---|---|
Short | Feature | Short | Feature | |
0 | fpu | Onboard x87 FPU | sse3 | Prescott New Instructions-SSE3 (PNI) |
1 | vme | Virtual 8086 mode extensions (such as VIF, VIP, PIV) | pclmulqdq | PCLMULQDQ |
2 | de | Debugging extensions (CR4 bit 3) | dtes64 | 64-bit debug store (edx bit 21) |
3 | pse | Page Size Extension | monitor | MONITOR and MWAIT instructions (SSE3) |
4 | tsc | Time Stamp Counter | ds-cpl | CPL qualified debug store |
5 | msr | Model-specific registers | vmx | Virtual Machine eXtensions |
6 | pae | Physical Address Extension | smx | Safer Mode Extensions (LaGrande) |
7 | mce | Machine Check Exception | est | Enhanced SpeedStep |
8 | cx8 | CMPXCHG8 (compare-and-swap) instruction | tm2 | Thermal Monitor 2 |
9 | apic | Onboard Advanced Programmable Interrupt Controller | ssse3 | Supplemental SSE3 instructions |
10 | (reserved) | cnxt-id | L1 Context ID | |
11 | sep | SYSENTER and SYSEXIT instructions | sdbg | Silicon Debug interface |
12 | mtrr | Memory Type Range Registers | fma | Fused multiply-add (FMA3) |
13 | pge | Page Global Enable bit in CR4 | cx16 | CMPXCHG16B instruction |
14 | mca | Machine check architecture | xtpr | Can disable sending task priority messages |
15 | cmov | Conditional move and FCMOV instructions | pdcm | Perfmon & debug capability |
16 | pat | Page Attribute Table | (reserved) | |
17 | pse-36 | 36-bit page size extension | pcid | Process context identifiers (CR4 bit 17) |
18 | psn | Processor Serial Number | dca | Direct cache access for DMA writes[7][8] |
19 | clfsh | CLFLUSH instruction (SSE2) | sse4.1 | SSE4.1 instructions |
20 | (reserved) | sse4.2 | SSE4.2 instructions | |
21 | ds | Debug store: save trace of executed jumps | x2apic | x2APIC |
22 | acpi | Onboard thermal control MSRs for ACPI | movbe | MOVBE instruction (big-endian) |
23 | mmx | MMX instructions | popcnt | POPCNT instruction |
24 | fxsr | FXSAVE, FXRESTOR instructions, CR4 bit 9 | tsc-deadline | APIC implements one-shot operation using a TSC deadline value |
25 | sse | SSE instructions (a.k.a. Katmai New Instructions) | aes | AES instruction set |
26 | sse2 | SSE2 instructions | xsave | XSAVE, XRESTOR, XSETBV, XGETBV |
27 | ss | CPU cache implements self-snoop | osxsave | XSAVE enabled by OS |
28 | htt | Hyper-threading | avx | Advanced Vector Extensions |
29 | tm | Thermal monitor automatically limits temperature | f16c | F16C (half-precision) FP feature |
30 | ia64 | IA64 processor emulating x86 | rdrnd | RDRAND (on-chip random number generator) feature |
31 | pbe | Pending Break Enable (PBE# pin) wakeup capability | hypervisor | Hypervisor present (always zero on physical CPUs)[9][10] |
Bit | EBX | ECX | EDX | |||
---|---|---|---|---|---|---|
Short | Feature | Short | Feature | Short | Feature | |
0 | fsgsbase | Access to base of %fs and %gs | prefetchwt1 | PREFETCHWT1 instruction | (reserved) | |
1 | IA32_TSC_ADJUST | avx512_vbmi | AVX-512 Vector Bit Manipulation Instructions | (reserved) | ||
2 | sgx | Software Guard Extensions | umip | User-mode Instruction Prevention | avx512_4vnniw | AVX-512 4-register Neural Network Instructions |
3 | bmi1 | Bit Manipulation Instruction Set 1 | pku | Memory Protection Keys for User-mode pages | avx512_4fmaps | AVX-512 4-register Multiply Accumulation Single precision |
4 | hle | TSX Hardware Lock Elision | ospke | PKU enabled by OS | fsrm | FSRM? |
5 | avx2 | Advanced Vector Extensions 2 | waitpkg | (reserved) | ||
6 | (reserved) | avx512_vbmi2 | AVX-512 Vector Bit Manipulation Instructions 2 | |||
7 | smep | Supervisor Mode Execution Prevention | shstk | |||
8 | bmi2 | Bit Manipulation Instruction Set 2 | gfni | Galois Field instructions | ||
9 | erms | Enhanced REP MOVSB/STOSB | vaes | Vector AES instruction set (VEX-256/EVEX) | ||
10 | invpcid | INVPCID instruction | vpclmulqdq | CLMUL instruction set (VEX-256/EVEX) | ||
11 | rtm | TSX Restricted Transactional Memory | avx512_vnni | AVX-512 Vector Neural Network Instructions | ||
12 | pqm | Platform Quality of Service Monitoring | avx512_bitalg | AVX-512 BITALG instructions | ||
13 | FPU CS and FPU DS deprecated | (reserved) | ||||
14 | mpx | Intel MPX (Memory Protection Extensions) | avx512_vpopcntdq | AVX-512 Vector Population Count Double and Quad-word | ||
15 | pqe | Platform Quality of Service Enforcement | (reserved) | |||
16 | avx512_f | AVX-512 Foundation | (reserved) | |||
17 | avx512_dq | AVX-512 Doubleword and Quadword Instructions | mawau | The value of userspace MPX Address-Width Adjust used by the BNDLDX and BNDSTX Intel MPX instructions in 64-bit mode | ||
18 | rdseed | RDSEED instruction | pconfig | Platform configuration (Memory Encryption Technologies Instructions) | ||
19 | adx | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) | (reserved) | |||
20 | smap | Supervisor Mode Access Prevention | ibt | |||
21 | avx512_ifma | AVX-512 Integer Fused Multiply-Add Instructions | (reserved) | |||
22 | pcommit | PCOMMIT instruction | rdpid | Read Processor ID | ||
23 | clflushopt | CLFLUSHOPT instruction | (reserved) | |||
24 | clwb | CLWB instruction | (reserved) | |||
25 | intel_pt | Intel Processor Trace | cldemote | |||
26 | avx512_pf | AVX-512 Prefetch Instructions | (reserved) | IBRS_IBPB / spec_ctrl | Speculation Control, part of Indirect Branch Control (IBC): Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Prediction Barrier (IBPB)[18][19] | |
27 | avx512_er | AVX-512 Exponential and Reciprocal Instructions | MOVDIR | stibp | Single Thread Indirect Branch Predictor, part of IBC[18] | |
28 | avx512_cd | AVX-512 Conflict Detection Instructions | MOVDIR64B | (reserved) | ||
29 | sha | Intel SHA extensions | (reserved) | capabilities | Speculative Side Channel Mitigations[18] | |
30 | avx512_bw | AVX-512 Byte and Word Instructions | sgx_lc | SGX Launch Configuration | (reserved) | |
31 | avx512_vl | AVX-512 Vector Length Extensions | (reserved) | ssbd | Speculative Store Bypass Disable,[18] as mitigation for Speculative Store Bypass |
Bit | EDX | ECX | ||
---|---|---|---|---|
Short | Feature | Short | Feature | |
0 | fpu | Onboard x87 FPU | lahf_lm | LAHF/SAHF in long mode |
1 | vme | Virtual mode extensions (VIF) | cmp_legacy | Hyperthreading not valid |
2 | de | Debugging extensions (CR4 bit 3) | svm | Secure Virtual Machine |
3 | pse | Page Size Extension | extapic | Extended APIC space |
4 | tsc | Time Stamp Counter | cr8_legacy | CR8 in 32-bit mode |
5 | msr | Model-specific registers | abm | Advanced bit manipulation (lzcnt and popcnt) |
6 | pae | Physical Address Extension | sse4a | SSE4a |
7 | mce | Machine Check Exception | misalignsse | Misaligned SSE mode |
8 | cx8 | CMPXCHG8 (compare-and-swap) instruction | 3dnowprefetch | PREFETCH and PREFETCHW instructions |
9 | apic | Onboard Advanced Programmable Interrupt Controller | osvw | OS Visible Workaround |
10 | (reserved) | ibs | Instruction Based Sampling | |
11 | syscall | SYSCALL and SYSRET instructions | xop | XOP instruction set |
12 | mtrr | Memory Type Range Registers | skinit | SKINIT/STGI instructions |
13 | pge | Page Global Enable bit in CR4 | wdt | Watchdog timer |
14 | mca | Machine check architecture | (reserved) | |
15 | cmov | Conditional move and FCMOV instructions | lwp | Light Weight Profiling[22] |
16 | pat | Page Attribute Table | fma4 | 4 operands fused multiply-add |
17 | pse36 | 36-bit page size extension | tce | Translation Cache Extension |
18 | (reserved) | |||
19 | mp | Multiprocessor Capable | nodeid_msr | NodeID MSR |
20 | nx | NX bit | (reserved) | |
21 | (reserved) | tbm | Trailing Bit Manipulation | |
22 | mmxext | Extended MMX | topoext | Topology Extensions |
23 | mmx | MMX instructions | perfctr_core | Core performance counter extensions |
24 | fxsr | FXSAVE, FXRSTOR instructions, CR4 bit 9 | perfctr_nb | NB performance counter extensions |
25 | fxsr_opt | FXSAVE/FXRSTOR optimizations | (reserved) | |
26 | pdpe1gb | Gibibyte pages | dbx | Data breakpoint extensions |
27 | rdtscp | RDTSCP instruction | perftsc | Performance TSC |
28 | (reserved) | pcx_l2i | L2I perf counter extensions | |
29 | lm | Long mode | (reserved) | |
30 | 3dnowext | Extended 3DNow! | (reserved) | |
31 | 3dnow | 3DNow! | (reserved) |
CPUID
must be issued with each parameter in sequence to get the entire 48-byte null-terminated ASCII processor brand string.[23] It is necessary to check whether the feature is present in the CPU by issuing CPUID
with EAX = 80000000h
first and checking if the returned value is greater or equal to 80000004h.<cpuid.h>
on systems that have CPUID. The __cpuid
is a macro expanding to inline assembly. Typical usage would be:<cpuid.h>
. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers.&a, &b, &c, &d
and the conditional statement. If the __get_cpuid
call receives a correct request, it will return a non-zero value, if it fails, zero.[25]__cpuid()
so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program for MSVC would be:CPUID
coprocessor register which requires EL1 or above to access.[26]STIDP
) instruction since the 1983 IBM 4381[27] for querying the processor ID.[28]PrId
) and a series of daisy-chained Configuration Registers.[29]PVR
) identifying the processor model in use. The instruction requires supervisor access level.[30]CPUID
to identify various system settingsIntel and AMD CPUs have reserved bit 31 of ECX of CPUID leaf 0x1 as the hypervisor present bit. This bit allows hypervisors to indicate their presence to the guest operating system. Hypervisors set this bit and physical CPUs (all existing and future CPUs) set this bit to zero. Guest operating systems can test bit 31 to detect if they are running inside a virtual machine.
Bit 31 of ECX of CPUID leaf 0x1. This bit has been reserved by Intel & AMD for use by hypervisors, and indicates the presence of a hypervisor. Virtual CPU's (hypervisors) set this bit to 1 and physical CPU's (all existing and future cpu's) set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine.